Generally, a power supply voltage detecting circuit of a semiconductor memory device is for detecting the changes of the power supply voltage applied to the interior of a chip, based on a specific voltage. When the voltage level of the power supply voltage applied to the interior of a chip is greatly changed, such a power supply voltage detecting circuit should be provided into semiconductor memory elements. This is well disclosed in U.S. Pat. Nos. 4,224,539 and 4,013,902.
FIG. 1 is a diagram showing a conventional power supply voltage circuit. The circuit includes diode-connected NMOS transistors 100 and 105 between a power supply voltage Vcc and a node N1, a resistor 115 between the node N1 and a ground voltage, and an invertor 110 between the node N1 and an output node N2.
As depicted in FIG. 1, the power supply voltage Vcc applied from an exterior is applied to the invertor 110 through the diode-connected NMOS transistors 100 and 105. When the power supply voltage Vcc passes through the diode-connected NMOS transistors 100 and 105, the voltage drops by the threshold voltage Vth of each of the respective diode-connected NMOS transistors 100 and 105. Accordingly, the voltage at the node N1 is Vcc-2Vth. If a low power supply voltage is applied to the power supply voltage detecting circuit of FIG. 1, since the voltage at the node N1 is lower than a logic threshold voltage of the inverter 110, the voltage level at the output node N2 becomes a logic "high" state. On the other hand, if a high power supply voltage is applied to the power supply voltage detecting circuit, the voltage level at the output node N2 becomes a logic "low" state.
In a conventional circuit however, in the case that the voltage at the node N1 has a intermediate value between the power supply voltages and the ground voltage, since a direct-current path is formed between a power supply voltage terminal and a ground voltage terminal of the inverter 110, there is a problem that the current flows even in a standby-state of a chip. Therefore, a current is continuously consumed. Further, when applying the low power supply voltage to the power supply voltage circuit, a operation speed of a chip is decreased. Moreover, when applying a high power supply voltage to the power supply voltage circuit, a chip effectivity is reduced a malfunction is generated due to the increased noise.